Structural VHDL Implementation of Wallace Multiplier

Scheming multipliers that are of high-speed, low power, and standard in design are of substantial research interest. By reducing the generated partial products speed of the multiplier can be increased. Several attempts have been made to decrease the number of partial products generated in a multiplication process. One of the attempt is Wallace tree multiplier. This paper aims at designing and implementation of Wallace tree multiplier. Speed of Wallace tree multiplier can be enhanced by using compressor techniques. By minimizing the number of half adders and full adders used in a multiplier reduction will reduce the complexity.